synopsys_crack.zip

synopsys_tarconfig.tar.gz - 16.46KBvcs_2012_32bitxa_vD-2010.03.tar.bz2 - 422.34MBverdi.tar.bz2 - 536.14MBvcs_vD-2010.06.tar.bz2 - 900.71MBvcs-mx_vC-2009.06.tar.bz2 - 633.13MBtars.bash - 1.66KBsynopsys2013.tar.bz2 - 3.81GB......

Synopsys工具(1)SystemVerilog Verification UVM 1.1 Student Guide.pdf - 91.15MBSystemVerilog Verification UVM 1.1 Lab Guide.pdf - 30.98MBSystemVerilog Testbench Student Guide.pdf - 60.23MBSystemVerilog Testbench Lab.tar - 290.00KBSystemVerilog Testbench Lab Guide.pdf - 24.05MBSynopsys_ICC_compiler_2011_Fast_Hierarchical_Design.pdf - 2.96MBICC GUI Demo - Hierarchical Design Planning.rar - 23.34MBIC Compiler 2 CTS Student Guide.pdf - 24.62MB......

DSC_7250.JPG - 8.10MBDSC_7249.JPG - 6.95MBDSC_7229.JPG - 7.13MBDSC_7210.JPG - 4.89MBDSC_2429.JPG - 9.99MBDSC_2424.JPG - 10.77MBDSC_2410.JPG - 10.86MBDSC_2409.JPG - 11.50MBDSC_2404.JPG - 11.59MB......